The present disclosure relates to semiconductor wafers, such as silicon wafers that are used as substrates for making photovoltaic devices.
One of the strategies for lowering the cost of silicon-based photovoltaic (PV) energy is to use thinner wafers for solar cell fabrication. This strategy reduces the wafer cost and increases solar cell efficiency, provided appropriate cell design and processing techniques are employed. Although the concept of reducing wafer thickness is quite straightforward, it is difficult to implement in manufacturing. The experience in the industry is that even for the current wafers, which have a nominal thickness of about 250 μm, the breakage during solar cell fabrication is quite high. The estimated fraction of wafers that break during cell fabrication and module encapsulation ranges between 5% and 10%. Additional reductions in the wafer thickness are found to further decrease the yield to unacceptable values.
The yield loss due to wafer breakage has a considerable influence on the economies of producing solar cells. In particular, because the loss in revenue associated with wafer breakage increases as the cell fabrication progresses, it is desirable to exclude those wafers that may break during cell processing from entering the fabrication lines. Identifying the sources of wafer breakage, understanding the wafer breakage mechanisms, and developing methods of detecting and separating these wafers that are susceptible to breakage is of value, especially at early stages of solar cell fabrication.
Wafer breakage is not a major issue in the semiconductor industry, which also uses silicon wafers. The semiconductor industry utilizes certain criteria for wafer preparation and processing, which minimize wafer breakage. These preventive measures add significant costs. The photovoltaic industry finds that it is not able to adopt these preventive measures due to the high cost that is associated with these procedures. Thus, the excessive breakage of wafers in the photovoltaic industry is primarily due to inadequate wafer preparation, inexpensive wafer handling, and low-cost device processing methods, which are all aimed at minimizing the cost of the solar cell. This incomplete wafer preparation in the photovoltaic industry leaves such as microcracks at the surfaces and the edges of the wafers, which lead to wafer breakage during cell fabrication as discussed later.
Optical methods are sometimes used in the industry to detect flaws in wafers. Japanese Patent No. JP11351850 discloses a method and apparatus for detecting a flaw on the end part of a semiconductor wafer using an optical system, which illuminates the edge and measures the scattered radiation by two detectors.
U.S. Pat. No. 6,861,268 discloses a method for inspecting a silicon wafer using a laser confocal microscope to identify and efficiently detect defects, a device fabricating process, a method for manufacturing a silicon wafer enabling manufacture of wafers not having the defect, a method for fabricating a semiconductor device using the silicon wafer not having this defect, and the silicon wafer not having the defect. When a silicon wafer is inspected, inspection is made for this new defect, having the entire defect size of 0.5 μm or more, in which microdefects gather in a colony state.
U.S. Pat. No. 6,807,454 discloses a bright field (BF) method for automatically controlling defect-specification in semiconductor manufacturing. The method provides a module to detect position, number, size, and intensity signals of defects on a processed patterned wafer. The module further compares the patterned wafer with a normal wafer to preliminarily classify the patterned wafer and creates a defect map. Then, a defect management system is provided to execute a spatial pattern recognition procedure to determine whether or not the corresponding special pattern can be recognized.
U.S. Pat. No. 6,816,251 discloses an electronic media edge defect detector in one form, having plural light sources and detectors arranged to direct and receive deflected light from the side edge margins and outer edge margins of the electronic media. The detected light is analyzed to determine the presence of defects. Individual wafers may be raised while in a cassette and turned during the inspection without removing the wafers from the cassette.
U.S. Pat. No. 6,604,853 discloses an accelerated thermal stress cycle test for semiconductor chips, which can be conducted in a reduced test time compared to the conventional test. The test is carried out in a cluster of reaction chambers that includes a CVD chamber and a cool-down chamber such that a pre-processed wafer can be heated from room temperature to at least 350° C. in an inert gas in about 2 min., and cooled down to not higher than 70° C. in a cool-down chamber in less than 30 sec. The heating and cooling steps can be repeated between 3 and 7 times to reveal any defect formation caused by the thermal stress cycle test. Typical defects are metal film peeling from insulating dielectric material layer or void formation.
The above-mentioned examples illustrate use of optical techniques to detect and identify defects or flaws in semiconductor wafers, which have polished surfaces. These techniques are difficult to use on photovoltaic wafers for detection of flaws and defects because these wafers have rough surfaces. The surface roughness “hides” such flaws and microcracks, making it difficult to recognize their presence by optical techniques. Optical excitation, as in rapid thermal processing, may also be used to heat the wafers for the purpose of wafer characterization.
U.S. Pat. No. 5,410,162 discloses an apparatus and a method for rapidly changing the temperature of a semiconductor wafer in an RTP processor in order to perform electrical tests at elevated temperature, and then cooling the wafer rapidly to ambient temperature. Electrical tests may be performed as desired during the process. Optical heating is typically employed to uniformly heat a semiconductor wafer.
Thus, it would be a significant contribution to the art to provide an effective method of rapidly screening wafers, which have defects that can result in the wafer breakage during device fabrication.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.